1. Field of the Invention
The present invention relates to a circuit for driving a display panel, particularly to a circuit configuration capable of reducing power consumption in driving a display panel for a plasma display, an electroluminescence display, a liquid crystal display (LCD), or the like, as a capacitive load, and relates to a display device to which the drive circuit is applied.
2. Description of the Related Art
FIG. 15 is a block diagram schematically showing a three-electrode surface-discharge plasma display panel of an AC drive type, and FIG. 16 is a cross sectional view for explaining the electrode structure of the plasma display panel shown in FIG. 15. In FIG. 15 and FIG. 16, the reference numeral 207 denotes discharge cells (display cells), 210 a rear glass substrate, 211 and 221 dielectric layers, 212 phosphors, 213 barrier ribs, 214 address electrodes (A1 to Ad), 220 a front glass substrate, and 222 X electrodes (X1 to XL) or Y electrodes (Y1 to YL), respectively. Note that the reference symbol Ca shows capacitances between adjacent electrodes in the address electrodes, and Cg shows capacitances between opposing electrodes (the X electrodes and the Y electrodes) in the address electrodes 214.
A plasma display panel 201 is composed of two glass substrates, the rear glass substrate 210 and the front glass substrate 220. In the front glass substrate 220, the X electrodes (X1, X2, to XL) and the Y electrodes (scan electrodes: Y1, Y2, to YL) constituted as sustain electrodes (including BUS electrodes and transparent electrodes) are disposed.
In the rear glass substrate 210, the address electrodes (A1, A2, to Ad) 214 are disposed perpendicularly cross the sustain electrodes (the X electrodes and the Y electrodes) 222. Each of the display cells 207 generating discharge light-emission by these electrodes is formed in a region which is sandwiched by the X electrode and the Y electrode, namely the sustain electrodes, assigned the same number (Y1-X1, Y2-X2, . . . ) and which intersects the address electrode.
FIG. 17 is a block diagram showing an overall configuration of a plasma display device using the plasma display panel shown in FIG. 15. It shows an essential part of a drive circuit for the display panel.
As shown in FIG. 17, the three-electrode surface-discharge plasma display panel of the AC drive type is composed of the display panel 201 and a control circuit 205 which generates control signals for controlling the drive circuit for the display panel by an interface signal which is inputted from the outside. The three-electrode surface-discharge plasma display device of the AC drive type is also composed of an X common driver (an X electrode drive circuit) 206, a scan electrode drive circuit (a scan driver) 203, a Y common driver 204, and an address electrode drive circuit (an address driver) 202, which are to drive panel electrodes by the control signals from the control circuit 205.
The X common driver 206 generates a sustain voltage pulse. The Y common driver 204 also generates a sustain voltage pulse. The scan driver 203 independently drives and scans each of the scan electrodes (Y1 to YL). The address driver 202 applies an address voltage pulse corresponding to display data to each of the address electrodes (A1 to Ad).
The control circuit 205 includes a display data control part 251 which receives a clock CLK and display data DATA and supplies an address control signal to the address driver 202, a scan driver control part 253 which receives a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync and controls the scan driver 203, and a common driver control part 254 which controls the common drivers (the X common driver 206 and the Y common driver 204). Incidentally, the display data control part 251 includes a frame memory 252.
FIG. 18 is a chart showing examples of drive waveforms of the plasma display device shown in FIG. 17. It schematically shows waveforms of applied voltages to the respective electrodes, mainly in a total write period (AW), a total erase period (AE), an address period (ADD), and a sustain period (a sustain discharge period: SUS).
In FIG. 18, drive periods directly involved in image display are the address period ADD and the sustain period SUS. A pixel to be displayed is selected in the address period ADD, and the selected pixel is caused to sustain light emission in the next sustain period so that an image is displayed with a predetermined brightness. Note that FIG. 18 shows the drive waveforms in each sub-frame when one frame consists of a plurality of the sub-frames (sub-fields).
First, in the address period ADD, an intermediate potential −Vmy is synchronously applied to all the Y electrodes (Y1 to YL) which are the scan electrodes. Thereafter, the intermediate potential −Vmy is changed over to a scan voltage pulse on −Vy level, which is applied to the Y electrodes (Y1 to YL) in sequence. At this time, an address voltage pulse on +Va level is applied to each of the address electrodes (A electrodes: A1 to Ad) in synchronization with the application of the scan pulse to each of the Y electrodes, thereby performing pixel selection on each scan line.
In the subsequent sustain period SUS, a common sustain voltage pulse on +Vs level is alternately applied to all of the scan electrodes (Y1 to YL) and the X electrodes (X1 to XL), thereby allowing the pixel which is previously selected to sustain the light emission. By this successive application, the display with a predetermined brightness is performed. Further, when the number of times of the light emissions is controlled by combining a series of the basic operations of the drive waveforms as described above, it is also made possible to display the tone of shading.
Here, the total write period AW is a period in which a write voltage pulse is applied to all of the display cells of the panel to activate each of the display cells and keep their display characteristics uniform. The total write period AW is inserted at a regular cycle. The total erase period AE is a period in which an erase voltage pulse is applied to all the display cells of the panel before an address operation and a sustain operation for image display are newly started, thereby erasing previous display contents.
FIG. 19 is a block circuit diagram showing one example of an IC which is used for the plasma display device shown in FIG. 17.
For example, when the display panel has 512 Y electrodes (Y1 to YL) and a drive IC connected to the Y electrode has 64 bit outputs, totally eight drive ICs are used. In general, the eight drive ICs are divided and mounted on a plurality of modules, on each of which a plurality of the ICs are mounted.
FIG. 19 shows a circuit configuration inside a drive IC chip 230 having output circuits (234: OUT1 to OUT64) for 64 bits. Each of the output circuits 234 is constituted in a manner that a high voltage power supply wire VH and a ground wire GND are connected with push-pull type FETs 2341 and 2342 of a final output stage therebetween. This drive IC 230 further has logic circuits 233 for controlling both of the FETs, a shift register circuit 231 for selecting the output circuits for 64 bits, and a latch circuit 232.
Their control signals are composed of a clock signal CLOCK and a data signal DATA for the shift register 231, a latch signal LATCH for the latch circuit 232, and a strobe signal STB for controlling gate circuits. The final output stage has a CMOS configuration (2341 and 2342) in FIG. 19, but a totempole configuration composed of MOSFETs having the same polarity can be also applied.
Next, an example of a method of mounting the above-described drive IC chip will be explained. For example, the drive IC chips are mounted on a rigid printed substrate, and pad terminals for a power supply, signals, and outputs of the drive IC chips and corresponding terminals on the printed substrate are connected by wire bonding.
Output wires from the IC chips are drawn out to an end surface side of the printed substrate to form output terminals. The output terminals are connected by thermocompression bonding to a flexible substrate, on which the same terminals are provided, to form one module. At a tip of this flexible substrate, a terminal for connection to panel display electrodes is provided. The terminal is connected to the panel display electrodes for use by a method such as thermocompression.
All of drive terminals of the respective electrodes described above, except dummy electrodes in an end part of the panel, are insulated from the ground potential of the circuits in terms of direct current, and capacitive impedance is dominant as a load of the drive circuits. A power recovery circuit to which energy transfer between a load capacitance and an inductance by a resonant phenomenon is applied is known as a technology for lowering power consumption of a pulse drive circuit of a capacitive load. A low power drive circuit described in Japanese Patent Laid-Open No. 5-249916 shown in FIG. 20 is an example of the power recovery circuit suitable for the drive circuit such as the address electrode drive circuit, in which the load capacitance greatly changes in order to drive individual load electrodes by the voltages independent of each other in accordance with a display image.
In the conventional example shown in FIG. 20, a power supply terminal 121 of an address drive IC 120 is driven through the use of a power recovery circuit 110 having resonant inductances 112P and 112N so that power consumption is reduced. The power recovery circuit 110 outputs a normal constant address drive voltage at the timing when address discharge is induced in the address electrodes of the plasma display panel. Then, a voltage of the power supply terminal 121 is lowered to the ground level before switching states of output circuits 122 in the address drive IC are changed over. At this time, resonance is generated between the resonant inductances 112P and 112N in the power recovery circuit 110 and a combined load capacitance (for example, CL×n at the largest) of any number (for example, n at the largest) of the address electrodes, which are being driven at high level, so that power consumption in output elements of the output circuits 122 in the address drive IC is greatly reduced.
In the conventional drive method in which the power supply voltage of the address drive IC is kept constant, the entire amount of change in stored energy in the load capacitance CL before and after the switching is consumed in a resistive impedance part in a charge/discharge current path. When the power recovery circuit 110 is used, a potential energy amount stored in the load capacitance with an intermediate potential of the address drive voltage, which is a resonant center of an output voltage, as a reference is maintained via the resonant inductances 112P and 112N of the power recovery circuit 110. After the switching states of the output circuits are changed over while the power supply voltage is at the ground, the power supply voltage of the address drive IC is raised again to the normal constant drive voltage through resonance so that power consumption is reduced.
Moreover, another technology for lowering power consumption of the pulse drive circuit of the capacitive load is a capacitive load drive circuit described in unpublished Japanese Patent Application No. 2000-301015 shown in FIG. 21. In this circuit, power is distributed to a power distributor 30 composed of a resistance and a constant current circuit to reduce power consumption of a drive element 6 in a drive circuit 3. This is based on a principle that a drive current flowing through the drive element 6 is also sent to the power distributor 30 connected in series so that power consumption is distributed at a sharing ratio corresponding to a voltage dividing ratio therebetween. Further, by raising and lowering a drive power supply 1 by n stages, supplied power from the drive power supply 1 to the drive circuit 3 and power consumption of each part in the drive circuit 3 can be also reduced to one-nth. In comparison to the power recovery technology described above, it is not necessary to induce the resonant phenomenon showing a high Q, and therefore a large load capacitance 5 can be driven at a high speed while reducing power consumption of the drive element 6 in the drive circuit 3 at the same level, which brings about an advantage that circuit costs can be substantially cut.
The conventional drive circuit shown in FIG. 20 described above intends to reduce power consumption through the use of the resonant phenomenon, but there is a problem that an effect of reducing power consumption is greatly lost as the recent plasma display panel has higher resolution and larger size. If an output frequency of the drive circuit is increased in response to the higher resolution, time for the afore-said resonance needs to be shortened in order to maintain control performance of the plasma display panel. At this time, only values of the resonant inductances provided in the power recovery circuit need to become smaller, which decreases the effect of power reduction due to decrease in Q of the resonance. Further, even if a parasitic capacitance of the address electrodes is increased as the screen becomes larger, the aforesaid effect of power reduction is decreased because of the decrease in the resonant inductance values described above in order to prevent the afore-mentioned resonant time from increasing. Furthermore, as the output frequency of the drive circuit is increased, the number of times the plasma display panel is driven by a high-voltage pulse is also increased, which increases power consumption and causes a big problem of heating in the drive circuit (the drive IC).
Also in the capacitive load drive circuit shown in FIG. 21, in which a power distribution method is used, if the supplied power from the drive power supply 1 to the drive circuit 3 can be further decreased, heating in the overall system including the power supply circuit can be reduced, which enables further cost reduction.
If power consumption of the drive circuit 3 cannot be reduced sufficiently, heatsinking costs and parts costs of each part in the display are increased. Further, there may arise a case in which light-emission brightness is restricted by heatsinking limitation of the display device itself or downsizing as an advantage of a flat panel display is not realized sufficiently.